The purpose of this study was to improve the repulsion ability of sulfonated poly(ether ether ketone) (SPEEK) membrane for the vanadium ions crossover. For this purpose graphene oxide (GO) nanosheet and titanium dioxide (TiO₂) nanoparticles were employed into the polymer matrix to prepare SPEEK/GO/TiO₂ hybrid membrane via solution-casting method for vanadium redox flow battery (VRFB). The morphology, permeability of vanadium ions and device performance of asprepared membrane were investigated and discussed. It was observed that with the barrier block effect by the filler, the VRFB single cell with the optimized SPEEK/GO/TiO₂ hybrid membrane exhibited high coulombic efficiency (~99%), excellent energy efficiency (~85%) and vigorous cyclability (~97.2% capacity retention after 100 cycles). Moreover, the VRFB cell with this blend membrane showed lower vanadium ions permeability than Nafion 212 or pure SPEEK membranes. These results demonstrated that the comprehensive properties of hybrid membrane have been remarkably improved comparing to pristine SPEEK which suggested that the hybrid membrane was applicable for VRFB energy storage system.In this work, we present a highly stretchable dry electrode composited with carbon nanofiber (CNF) for wearable device by simple method. The fabricated electrodes were assembled with snap connector for connect with electric circuit and sticky polymer for improving adhesion strength on the skin. We evaluated the electrical and mechanical properties depending on the weight % (wt%) and thickness of CNF/elastomer composited stretchable electrode. From the results, the electrical characteristic was improved as increasing concentrations of CNF and their dropping volume. And we evaluated a stretchability and electromechanical property using with cycling test. Through these tests, we have demonstrated that fabricated dry electrode has outstanding stretchability and durability under stretching condition. Finally, electrocardiogram (ECG) was measured with these electrodes. The results of ECG measurement showed similar or larger signal that of commercial wet electrode. Consequently, these results are expected to apply as a wearable device such as a bio-signal measurement and strain sensors.We investigated the effect of graphene quantum dots (GQDs) on performance of single-junction Ge solar cell grown on (100) substrate by low pressure metalorganic chemical vapor deposition (LP-MOCVD). Isobutylgermane (IBuGe) is used as a Ge precursor for the Ge solar cell growth. By employing GQDs, the power conversion efficiency of the Ge solar cell is improved up to 3.90% (Voc of 0.22 V, Jsc of 28.52 mA/cm², and FF of 63.83%) through effective photon management as compared to bare Ge solar cells of 3.24% under AM 1.5G illumination.In this work, noise mechanism of a tunneling field-effect transistor (TFET) on a silicon-on-insulator substrate was studied as a function of temperature. The results show that the drain current and subthreshold slope increase with increase in temperature. This temperature dependence is likely caused by the generation of greater current flow owing to decreased silicon band gap and leakage. Further, the TFET noise decreases with increase in temperature. Therefore, the effective tunneling length between the source and the channel appears to decrease and Poole-Frenkel tunneling occurs.This paper proposes the core insulator nano-sheet transistor structure for improved electrostatic characteristics by adding an oxidation process to the conventional Nano-sheet field effect transistor process. The additional insulated core improves the drain induced barrier lowering and the subthreshold slope properties by enhancing the gate controllability. The major advantage of the proposed structure is that it can be fabricated using the conventional nano-sheet field effect transistor process by simply adding another oxidation step. We compared the performance of our proposed device to that of FinFET and nano-sheet field effect transistor at sub 3 nm node using technology computer-aided design simulation. An optimal device structure including the oxide thickness and channel stacking is suggested with consideration for drive current, leakage and electrostatic characteristics.In this paper, we investigated the threshold voltage (Vth) variations in sub 5-nm node silicon nanosheet FETs (NSFETs) caused by Ge and C diffusion into NS channels using fully-calibrated 3-D TCAD simulation. Ge (C) atoms of Si1-xGex (Si1-xCx) source/drain (S/D) diffuse toward the NS channels in lateral direction in p-type (n-type) FETs, and Ge atoms of Si0.7Ge0.3 stacks diffuse toward the NS channels in vertical direction. Increasing Ge mole fraction of the Si1-xGex S/D in the p-type FETs (PFETs) causing increasing compressive channel stress retards boron dopants diffusing from the Si1-xGex S/D into the NS channels, thus increasing the Vth of PFETs (Vth, p). However, the Vth, p decreases as the Ge mole fraction of the Si1-xGex S/D becomes greater than 0.5 due to the higher valence band energy (Ev) of the NS channels. S3I-201 order On the other hand, the Vth of n-type FETs (NFETs) (Vth, n) consistently increases as the C mole fraction of the Si1-xCx S/D increases due to monotonously retarded phosphorus dopants diffusing from the Si1-xCx S/D into the NS channels. On the other hand, the Vth, p and Vth, n consistently decreases and increases, respectively, as Si/Si0.7Ge0.3 intermixing becomes severer because both Ev and conduction band energies (Ec) of the NS channels become higher. In addition, the Vth, p variations are more sensitive to the Si/Si0.7Ge0.3 intermixing than the Vth, n variations because the Ge mole fraction in NS channels affects the Ev remarkably rather than the Ec. As a result, the Ge atoms diffusing toward the NS channels should be carefully considered more than the C diffusion toward the NS channels for fine Vth variation optimization in sub 5-nm node NSFETs.In this work, we present a normally-off recessed-gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) using a TiO₂/SiN dual gate-insulator. We analyzed the electrical characteristics of the proposed device and found that the dual gate-insulator device achieves higher on-state currents than the device using a SiN gate-insulator because the high-k insulator layer of the dual gate-insulator improves the gate-controllability. The device using a TiO₂/SiN gate-insulator shows better gate leakage current characteristics than the device with only TiO₂ gate-insulator because of the high quality SiN gate-insulator. Therefore, the device using a dual gate-insulator can overcome disadvantages of a device using only TiO₂ gate-insulator. To better predict the power consumption and the switching speed, we simulated the specific on-resistance (Ron, sp) according to the gate-to-drain distance (LGD) using the two-dimensional ATLAS simulator. The proposed device exhibits a threshold voltage of 2.